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| SL74HCT14 Hex Schmitt-Trigger Inverter High-Performance Silicon-Gate CMOS The SL74HCT14 may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The SL74HCT14 is identical in pinout to the LS/ALS14. The SL74HCT14 is useful to "square up" slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the SL74HCT14 finds applications in noisy environments. * TTL/NMOS-Compatible Input Levels. * Outputs Directly Inferface to CMOS, NMOS and TTL. * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION SL74HCT14N Plastic SL74HCT14D SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs A L H Output Y H L PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor SL74HCT14 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter DC Supply Voltage (Referenced to GND) VIN, VOUT TA tr, t f * Min 4.5 0 -55 0 Max 5.5 VCC +125 No Limit* Unit V V C ns DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) When VIN 50% VCC ,ICC>1.0 mA. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT14 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.98 0.1 0.1 0.26 0.1 1.0 85 C 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.84 0.1 0.1 0.33 1.0 10 125 C 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.7 0.1 0.1 0.4 1.0 40 A A V Unit VT+max Maximum PositiveGoing Input Threshold Voltage Minimum PositiveGoing Input Threshold Voltage Maximum NegativeGoing Input Threshold Voltage Minimum NegativeGoing Input Threshold Voltage Maximum Hysteresis Voltage Minimum Hysteresis Voltage Minimum High-Level Output Voltage VOUT=0.1 V IOUT 20 A VOUT=0.1 V IOUT 20 A VOUT=VCC -0.1 V IOUT 20 A VOUT=VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1V IOUT 20 A VOUT=0.1 V or VCC-0.1V IOUT 20 A VINVT -min IOUT 20 A VINVT -min IOUT4mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V VT+min V VT-max V VT-min V VHmax Note 1 VHmin Note 1 VOH V V V VOL Maximum Low-Level Output Voltage VINVT +max IOUT 20 A VINVT +max IOUT 4mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND VIN=VCC or GND IOUT=0A VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0 A ICC -55 C 5.5 2.9 25C to 125 C 2.4 mA Note: 1 VHmin>(VT+min)-(VT-max); VHmax=(VT+max)-(VT-min) SLS System Logic Semiconductor SL74HCT14 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Temperature Limits Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A or B to Output Y (L to H) (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Power Dissipation Capacitance (Per Inverter) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 C to -55C 32 85C 40 125C 48 Unit ns tTLH, t THL CIN 15 10 19 10 Typical @25C,VCC=5.0 V 32 22 10 ns pF pF Figure 1. Switching Waveforms Figure 2. Test Circuit SLS System Logic Semiconductor |
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